TTEP @ ITC 2010 - Call for Participation

Advance Registration Deadline October 1st, 2010!

CALL FOR PARTICIPATION

Scope -- Key Dates -- Venue -- Workshop Registration -- Advance Program -- Test Clinic

Scope

The Tutorials & Education Group of the IEEE Computer Society Test Technology Technical Council (TTTC) organizes a comprehensive set of Test Technology Tutorials to be held in conjunction with several TTTC-sponsored technical meetings worldwide. The mission of the Test Technology Educational Program (TTEP) is to serve test and design professionals by offering fundamental education and expert knowledge in state-of-the-art test technology topics. TTEP offers tutorial participants the opportunity to earn official certification from IEEE Computer Society TTTC. Each full-day tutorial corresponds to four TTEP units. Upon completion of sixteen TTEP units, official recognition in the form of an IEEE TTTC Test Technology Certificate will be presented to the participant. For further information regarding TTEP, please visit http://tab.computer.org/tttc/teg/ttep/

At ITC 2010, TTTC/TTEP is pleased to present twelve full-day tutorials on topics of current interest to test professionals and researchers and a test clinic geared toward students and newcomers to test. All tutorials qualify for credit towards IEEE TTTC certification under the TTEP program. Five tutorials are held on Sunday, October 31. Seven tutorials will be held on Monday, November 1st. Each tutorial requires a separate registration fee (see ITC registration form or www.itctestweek.org for further information). Admission for on-site registrants is subject to availability.

Tutorial attendees receive study material, breakfast, lunch, and coffee breaks. The study material includes a hardcopy of the presentation and bibliographical material. Tutorial registration, coffee and pastry are available at 7:00 a.m. on Sunday and Monday.

Key Dates

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Advance Registration Deadline: October 1st 2010!

The Venue

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The ITC conference and all associated Test Week events will be held at the Austin Convention Center, Austin, Texas. Austin is the capital of the state of Texas, and its 1888 capitol building is an interesting landmark. Also of interest are the main campus of The University of Texas and the Lyndon B. Johnson Library and Museum. Close to the convention center is the lively East Sixth Street entertainment district which features many restaurants and a variety of music in the ―Live Music Capital of the World‖. The downtown area has miles of waterfront trails suitable for walking and jogging and is also home to the largest urban bat population in the US whose spectacular flight can be observed just before sunset. For more information about Austin, visit http://www.austintexas.org. Lodging for Test Week is in several hotels in the vicinity of the convention center.

Registration

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On-line Registration

Advance Program

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Sunday -- Monday

October 31, 2010 (Sunday)

8:30 AM - 4:30 PM	TUTORIAL 1 - Practices in Analog, Mixed-Signal and RF Testing Presenters: S. Abdennadher, S. Shaikh

8:30 AM - 4:30 PM	TUTORIAL 2 - Parameter Variations and Low-Power Design: Test Issues and On-Chip Calibration/Repair Solutions Presenters: R. Rao, S. Mukhopadhyay, S. Bhunia, P. Elakkumanan

8:30 AM - 4:30 PM	TUTORIAL 3 - High-Quality and Low-Cost Delay Testing for VDSM Designs: Challenges and Solutions Presenters: M. Tehranipoor, K. Chakrabarty, J. Rearick

8:30 AM - 4:30 PM	TUTORIAL 4 - Reliability, Availability and Serviceability of Networks-on-Chip Presenters: E. Cota, M. Lubaszewski

8:30 AM - 4:30 PM	TUTORIAL 5 - The Economics of Test and Testability Presenters: S. Davidson, H. Colby, L. Ungar

November 1, 2010 (Monday)

8:30 AM - 4:30 PM	TUTORIAL 6 - Testing Low-Power Integrated Circuits: Challenges, Solutions, and Industry Practices Presenters: S. Ravi, R. Kapur, M. Tehranipoor

8:30 AM - 4:30 PM	TUTORIAL 7 - Testing TSV-based 3-D Stacked ICs Presenters: E J. Marinissen, Y. Zorian

8:30 AM - 4:30 PM	TUTORIAL 8 - The Convergence and Inter-relationship of Yield, Design for Manufacturability and Test Presenters: S. Venkataraman, R. Aitken

8:30 AM - 4:30 PM	TUTORIAL 9 - Statistical Adaptive Test Methods Targeting "Zero Defect" IC Quality and Reliability Presenter: A. Singh

8:30 AM - 4:30 PM	TUTORIAL 10 - Bridge to Moore—IEEE Standards Provide Access to Debug, Validation and Test of Ever More Complex ICs—On ATE, on Board, in System Presenters: A. Ley, A. Crouch

8:30 AM - 4:30 PM	TUTORIAL 11 - Post-Silicon Validation and Debug Presenters: N. Nicolici, J. Stinson, B. Vermeulen

8:30 AM - 4:30 PM	TUTORIAL 12 - Post-Silicon Validation and Debug Presenters: N. Nicolici, J. Stinson, B. Vermeulen

TTTC/TTEP TEST CLINIC

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In addition to the regular tutorials, TTTC/TTEP is offering at ITC 2010 a Test Clinic, particularly geared towards newcomers to the area of test, such as new test engineers and students pursuing graduate studies in test. Its key objective is to offer a broad yet comprehensive review of basic test topics in an accessible way to the lay audience. This year’s topic will be Logic and Memory Testing for SOCs.

The Test Clinic will be a full-day event. Upon its completion, an official recognition in the form of an IEEE TTTC Test Technology Certificate will be presented to each participant.

For further information regarding TTEP, please visit http://tab.computer.org/tttc/teg/ttep/ The Test Clinic requires a separate registration fee (see ITC registration form or www.itctestweek.org for further information). Admission for on-site registrants is subject to availability.

Test Clinic attendees receive study material, breakfast, lunch, and coffee breaks. The study material includes a hardcopy of the presentation and bibliographical material. Test Clinic registration, coffee and pastry are available at 7:00 a.m. on Monday.

8:30 AM - 4:30 PM

TEST CLINIC Logic and Memory Testing for SOCs
Presenters: A. Cron, Y. Zorian

Testability is a fundamental requirement for today’s systems-on-chip. These integrated circuits are typically designed based on intellectual property (IP) block integration to make the best use of millions of gates available. Logic and memory IP blocks require adequate fault detection, silicon debug and yield optimization. All of which are based on testability infrastructure build into the systems-on-chip. This tutorial presents the fundamental knowledge base that any designer or testability engineer must have in order to fulfill the current industrial best practices for design-for-testability. The tutorial discusses the requirements for block-level test architecting, at-speed design practices, scan compression, memory self-test, debug and repair, test interface standardization efforts such as IEEE Std 1149.1 (JTAG) and IEEE Std. 1500, and integration for system-on-chip level and beyond. Actual industrial experiences will be shared with the audience whenever possible.

For more information, visit us on the web at:http:/www.itctestweek.org

TTEP is sponsored by the Institute of Electrical and Electronics Engineers (IEEE) Computer Society's Test Technology Technical Council (TTTC).